As CMOS transistor devices scale down, methods of improving circuit performance are increasingly important. One of the approaches in doing so is to enhance carrier mobilities in the channel region; i.e., increase in electron and hole mobility. This can be done by several methods:
1. Different Si lattice dimensions over a silicon substrate is used to obtain strain. Generally, strained-silicon on a relaxed SiGe buffer or strained-silicon on SOI (SSDOI) have shown electron mobility enhancement of about 2× on a N-FET and hole mobility enhancement of 50% on a P-FET at high Ge concentration SiGe alloy. It is largely due to silicon under biaxial tensile strain. However, most of this tensilely strained-Si consists of a high density of defects.
2. MOSFETs fabrication over different surface orientation silicon such as Si<110> substrate has shown ˜1.5× hole mobility enhancement in P-FET but electron mobility from N-FET is degraded substantially. A hybrid orientation substrate was described by Min Yang at the IEDM 2003 which combined a Si <110> substrate and Si <100> substrate together, so that the P-FET is built on Si<110> for hole mobility enhancement and N-FET is built on Si<100> to maintain the N-FET performance.
There is a need for a solution to obtain both hole and electron carrier enhancement in CMOS.